We are determined to

RTL Design & Verification Flow

Originality

Every project is unique, so we provide specific solutions for each of them

Creative Idea

Working with Custom Chip Logic/IP Core/Verification IP in project we are not afraid of fresh ideas and original solutions

Support

We always work together with the Partner and the Customer. Together we can overcome difficulties in the project. Is verification making troubles? Stuck with RTL design? We will help out

Professionals

In addition to daily development practice, we usually improve our knowledge, make researches in field of our interests. We regularly visit seminars in fields of RTL design and Verification

Development

Our developers are capable of SystemVerilog/Verilog/VHDL/С/С++/SystemC and use them actively developing our projects

Clean Code

We follow the Style Guides, always keep our code clear and reusable during development of each project

About us

Greetings!

A team of experienced and talented engineers, graduated from National Research Nuclear University MEPhI. We are united by common goals and look for new knowledge and challenges.

Everyone in our team is specialist in digital curcitry and verification. Together we can solve wide range of tasks, but when project involves us into a new topic, we thoroughly immerse ourself into it.

Every new problem makes us more experienced. We have already successfully completed dozens of projects and participated in the development of modern SoC.

We won't stop developing and mastering modern technologies. Customers appreciate our energy and ambitiousness. We always help customers in creating their own innovative products. We generate intellectual property for them and implement their ideas.

Best regards,
OhT team

1. By type of work

a. RTL Design
25%
b. Verification
75%

2. By product type

a. IP Cores
30%
b. Custom Chip Logic
25%
c. Verification IPs (VIP)
45%

3. By development languages

a. С++/SystemC
30%
b. SystemVerilog / Verilog
60%
c. VHDL / VHDL-2008
10%

Our Projects & Solutions

During passed 15 years, we have completed more than 50 projects.
Here you can find the most significant:

Video compression H.264(AVC)

Deblocking Filter IP Core

Data processing algorithms - H.264, High Profile, Level 4.2. Target technology - FPGA & ASIC.
Languages - VHDL for RTL & SystemC for Testbench. Verification: golden model methodology; SW/HW cosimulation model based methodology; SW/HW cosimulation

Rangefinder

Logic control and data processing

Target technology - FPGA. Languages - VHDL. Verification: assertion–based verification; block–level simulation

Network Router Search Processor

Design from scratch

Target technology - FPGA. Languages - Verilog for RTL & SystemVerilog for Testbench. Verification: SystemVerilog–UVM; golden data simulation; code coverage

Network firewall redundant link logic

Design from scratch

Target technology - FPGA. Languages - VHDL-2008 for RTL & SystemVerilog for Testbench. Verification: SystemVerilog–UVM; reusable verification components(VIP); constrained random tests(CRT); external SoC software emulation; error injection

SoC Peripheral subsystem verification

Portable tests + barmetal drivers design and verification

Target technology - ASIC. Languages - Systemverilog for testbench environment & C++ for tests and drivers. Verification: SV-UVM, peripheral VIPs; assertion–based verification; constrained random tests (CRT); platform independed tests; RTL & NETLIST simulation; code coverage

ARM Amba AXI3 communicator IP Core

Design from scratch

Target technology - FPGA.Languages - VHDL. Verification: assertion–based verification; block–level simulation; constrained random tests(CRT)

Video Interfaces VIPs

Design form scratch

Supported interfaces - CameraLink, Camera Serial Interface (CSI-2), CompositVideo, Custom Sensor RAW Data Interface, VGA, RGB, DVI, TV. Language - SystemVerilog. Verification: SystemVerilog–UVM; assertion–based verification; constrained random tests (CRT). Additional: configurative environment, image pattern generation

Avionics Control logic

Verification environment and tests

Target technology - FPGA. Languages - SystemVerilog.Verification: systemVerilog–UVM;
assertion–based verification; constrained random tests
(CRT); functional coverage

Our team

Engineers that ready to help with Your projects

Alexey Khaylov

CEO & co-founder

MSc: Department "Computer Systems and Technologies" MEPhI
Graduated in 2001

Alexey Overtchenko

CTO & co-founder

MSc: Department "Computer Systems and Technologies" MEPhI
Graduated in 2002

Andrey Skitev

Senior ASIC Verification Engineer

MSc: Department "Computer Systems and Technologies" MEPhI
Graduated in 2012

Yuliya Polovneva

Middle Verification Engineer

MSc: Department "Computer Systems and Technologies" MEPhI
Graduated in 2022

Evgeny Potapov

Middle Verification Engineer

Master Student: Department "Computer Systems and Technologies" MEPhI
Graduation in 2023

Pavel Burtsev

Middle Software Engineer

Specialist: Department "Automatic control systems" BMTSU
Graduated in 2022

Daniil Tsymbal

Trainee

Bachelor Student: Department "Computer Systems and Technologies" MEPhI
Graduation in 2025

Airat Mahmutov

Trainee

Bachelor Student: Department "Computer Systems and Technologies" MEPhI
Graduation in 2024

15

years of experience in
RTL Design & Verification

50

and more successful projects

10

partners

20

millon lines of working code

Contact Us

Any questions and suggestions are welcome.

In case the machines take over the World